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/1//2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR
ICS87421I
GENERAL DESCRIPTION
The ICS87421I is a high perfor mance /1//2 IC S Differential-to-LVDS Clock Generator and a memHiPerClockSTM ber of the HiPerClockSTM family of High Performance Clock Solutions from IDT. The CLK, nCLK pair can accept most standard differential input levels. The ICS87421I is characterized to operate from a 3.3V power supply. Guaranteed part-to-part skew characteristics make the ICS87421I ideal for those clock distribution applications demanding well defined performance and repeatability.
FEATURES
* One differential LVDS output * One differential CLK, nCLK input pair * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Maximum clock input frequency: 1GHz * Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVDS levels with resistor bias on nCLK input * Part-to-part skew: 500ps (maximum) * Propagation delay: 1.7ns (maximum) * Additive phase jitter, RMS @ 155.52MHz: 0.17ps (typical) * Full 3.3V operating supply * -40C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
BLOCK DIAGRAM
CLK nCLK
PIN ASSIGNMENT
/1 0 1
Q nQ CLK nCLK MR F_SEL 1 2 3 4 8 7 6 5 VDD Q nQ GND
R /2
MR
ICS87421I
8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View
F_SEL
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TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 Name CLK nCLK MR Input Input Input Type Pullup Description Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true output (Q) to go low and the inver ted output Pulldown (nQ) to go high. When logic LOW, the internal dividers and the output are enabled. LVCMOS / LVTTL interface levels. See Table 3. Selects divider value for Q, nQ outputs as described in Table 3. Pulldown LVCMOS / LVTTL interface levels. Power supply ground. Differential output pair. LVDS interface levels. Positive supply pin.
4 5 6, 7 8
F_SEL GND Q, nQ VDD
Input Power Output Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
TABLE 3. FUNCTION TABLE
MR 1 0 0 F_SEL X 0 1 Divide Value Reset: Q output low, nQ output high /1 /2
CLK
MR
Q
FIGURE 1A. /1 CONFIGURATION TIMING DIAGRAM
FIGURE 1B. /2 CONFIGURATION TIMING DIAGRAM
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5 V 10mA 15mA -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 96C/W (0 mps)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 55 Maximum 3.465 Units V mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol Parameter VIH VIL IIH IIL Input High Voltage Input Low Voltage Input High Current Input Low Current MR, F_SEL MR, F_SEL VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -5 Test Conditions Minimum 1.37 -0.3 Typical Maximum VDD + 0.3 0.7 15 0 Units V V A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD= 3.465V, VIN = 0V -5 -150 0.15 GND + 0.5 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage Common Mode Input Voltage; VCMR NOTE 1 NOTE 1: Common mode voltage is defined as VIH.
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TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change 1.1 1.25 Test Conditions Minimum 350 Typical 470 Maximum 540 50 1.4 50 Units mV mV V mV
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol fCLK tPD t sk(pp) t JIT t R / tF Parameter Clock Input Frequency Propagation Delay; CLK to Q (Dif) NOTE 1 Par t-to-Par t Skew; NOTE 2, 3 Additive Phase Noise, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time Test Conditions Minimum Typical Maximum 1 1.0 1.7 500 155.52MHz, Integration Range: 12kHz - 20MHz 20% to 80% 0.17 150 500 57 Units GHz ns ps ps ps %
odc Output Duty Cycle fIN < 500MHz 43 NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 155.52MHz (12kHz to 20MHz) = 0.17ps typical
SSB PHASE NOISE dBc/HZ
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device
meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
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PARAMETER MEASUREMENT INFORMATION
3.3V
VDD
SCOPE
3.3V5% POWER SUPPLY + Float GND -
VDD
Qx
nCLK V
PP
Cross Points
V
LVDS
nQx
CMR
CLK
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
PART 1 nQx Qx PART 2 nQy Qy
tsk(pp)
DIFFERENTIAL INPUT LEVEL
nCLK CLK nQ Q
tPD
PART-TO-PART SKEW
PROPAGATION DELAY
nQ 80% 80% VSW I N G Q
t PW
t
PERIOD
Clock Outputs
20% tR tF
20%
odc =
t PW t PERIOD
x 100%
OUTPUT RISE/FALL TIME
VDD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD out
out
DC Input
LVDS
100
VOD/ VOD
out
out
VOS/ VOS
DIFFERENTIAL OUTPUT VOLTAGE SETUP
OFFSET VOLTAGE SETUP
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DC Input
LVDS
ICS87421I /1//2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS:
LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
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DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY AN IDT OPEN EMITTER HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
2.5V
3.3V
2.5V 3.3V 2.5V
*R3
33
Zo = 50
R3 120 Zo = 60
R4 120
CLK
CLK
Zo = 50 nCLK
Zo = 60 nCLK
HCSL
*R4
33 R1 50 R2 50
HiPerClockS Input
SSTL
R1 120 R2 120
HiPerClockS
*Optional - R3 and R4 can be 0
FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER
FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER
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LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs.
3.3V 3.3V 50
LVDS Driver R1 100
+
-
50
100 Differential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS87421I. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS87421I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
*
Power_MAX = VDD_MAX * IDD_MAX = 3.465V * 55mA = 198.58mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 96C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.199W * 96C/W = 104.1C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
8-PIN SOIC, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 96C/W
1
87C/W
2.5
82C/W
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RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
8 LEAD SOIC
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 96C/W
1
87C/W
2.5
82C/W
TRANSISTOR COUNT
The transistor count for ICS87421I is: 417
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PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUN 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
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TABLE 9. ORDERING INFORMATION
Part/Order Number ICS87421AMI ICS87421AMI ICS87421AMILF ICS87421AMIFT Marking 87421AMI 87421AMI 87421AIL 87421AIL Package 8 lead SOIC 8 lead SOIC 8 lead "Lead-Free" SOIC 8 lead "Lead-Free" SOIC Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Corporate Headquarters
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Europe
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(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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